To ensure proper operation and high-quality of ICs, manufacturing tests must be run on fabricated devices to detect structural faults and eliminate defective parts or devices. Test patterns for a manufacturing test of an IC design are typically generated using an automatic test pattern generation (ATPG) tool. A conventional test pattern generation requires performing logic simulation of an IC design, typically using a gate-level description of the IC design. The gate-level description of the IC design is typically obtained by logic synthesis of a register-transfer-level (RTL) description of the IC design. An ATPG tool captures input stimuli and output responses during the logic simulation of the IC design and creates test vectors. However, as a circuit design becomes larger and more complex, such logic simulation requires a large number of simulation cycles, and the test pattern generation may take a significantly long time, for example, several days or more.
An IC design is also verified before its physical implementation. A verification of an IC design typically involves a simulation of the IC design. Two types of simulations may be used to verify the IC design: functional simulation and timing simulation. OpenVera™ is an open source hardware verification language (HVL) developed for functional verification of IC hardware designs, originally by Synopsys, Inc. of Mountain View, Calif. OpenVera™ is an object-oriented hardware verification language and enables circuit designers to create reusable objects that can be implemented using high level language and abstract data-structures, rather than low-level, register-transfer-level language (RTL) constructs. OpenVera™ also supports many features of both hardware description language (HDL) such as Verilog and general computer language such as C or C++.
OpenVera-based verification programs run in conjunction with a HDL simulator. OpenVera™ has the capability of separating the interface of an object from its implementation, and OpenVera-based verification programs can be separately compiled and dynamically linked to the HDL simulator. FIG. 1 schematically illustrates conventional verification of an IC design (Design Under Test) 10 using an OpenVera based verification program 20. The IC design 10 is described in a HDL, for example, Verilog (HDL representation). The verification program 20 includes a stimulus generation module (stimulus generator) 22, an expected-response generation module (expected-response generator) 24, and a comparator 26. The stimulus generator 22 operates at a higher level of abstraction, and automatically generates stimuli for the IC design 10 which is simulated by a HDL simulator. The expected-response generator 24 also operates at a higher level of abstraction and typically implements some reference model of the IC design 10 to generate the expected-responses. The comparator 26 compares output signals from the simulated IC design 10 against the expected-responses, and checks if they match. Then the verification program 20 outputs the comparison result (match or mismatch).
As shown in FIG. 1, the IC design 10 has input ports 30, in/out ports 32, and output ports 34. An interface 36 of the verification program provides signal-level connectivity into the HDL representation of the IC design 10, and also defines ports (signal directions) of the IC design 10. Since the functional verification only needs to monitor the output signals from the HDL simulator (simulating the IC design 10), the verification program 20 only samples signals from the in/out ports 32 and from the output ports 34 of the IC design 10.